#### Time domain analysis of capacitor voltage self-balance mechanism Part 2

This article analyzes the characteristics of the current i_{x}(t) and its average value I_{x(avg)} from the midpoint of the capacitor arm when V_{d}=0 and V_{d}≠0.

(1) V_{d}=0

V_{d}=0 means that the capacitor voltage is balanced. At this time, i_{inv}(t) is denoted as i_{i}_{nv_b}(t), and its expression is:

Among them, φ_{Zmn} is the impedance angle of Z_{e}_{q}, and φ_{Zmn}∈[-π/2,π/2], m=0,1,2,3,…,n=±1,±3,±5…

It can be seen from equation (1.1) that i_{inv_b}(t) only contains odd harmonics, while Figure 1 shows that S_{d} contains only DC components and even harmonics. According to formula (1.2) ix=-i_{inv}S_{d}, the average value I_{x}_{(aveg)_b} of the current i_{x}(t) out of the midpoint of the capacitor bridge arm is:

From equations (1.3) and (1.4), it can be seen that the average current of capacitors C_{dc1} and C_{dc2}: I_{1 (avg)} = I_{2 (avg)} = 0, which shows that when the capacitor voltage of 3L-NPC is balanced, there are:

① The average value of the current flowing out of the midpoint of the capacitor bridge arm is 0:

② There is no DC component in the capacitor current, and the average value of the capacitor voltage will stabilize at U_{dc}/2;

③Factors such as load nature and capacitance deviation do not affect the equilibrium state of capacitor voltage.

(2) V_{d}≠0.

V_{d}≠0 means that the capacitor voltage is not balanced. At this time, i_{inv}(t) is recorded as i_{inv_b}(t), and its expression is rewritten as formula (1.5):

Then the current i_{inv-nb}(t) consists of two parts, i_{inv-}_{b}(t) and i_{inv-}_{d}(t), i_{inv-}_{b}(t) is shown in formula (1.1), i_{inv-d}(t) is:

It can be seen from equation (1.6) that i_{inv-}_{d}(t) contains DC components and even harmonics. It also shows that when the capacitor voltage is unbalanced, the current i_{inv-nb}(t) before filtering contains a DC component, which is recorded as i_{inv-nb(avg)}, and its magnitude is:

Therefore, when the capacitor voltage is unbalanced, the average value I_{x(}_{avg}_{)_nb} of the current i_{x}(t) flowing out of the midpoint of the capacitor bridge arm is:

Combining formula (1.3) with formula (1.6) and the property that the product of different trigonometric functions is zero in one cycle, we can get:

Among them, φZmn is the impedance angle of Zeq, and φZmn∈[-π/2, π/2], m=0, 1, 2, 3., n=0, ±2, ±4….

From the formula (1.9), it can be seen that the magnitude of I_{x(avg)_nb} is derived from the contribution of the two properties of the bridge arm output current i_{inv}(t), which are the DC component and even harmonic components of i_{inv}(t) respectively, where K_{dc} and K_{harm} are respectively:

According to formula (1.9) and formula (1.4), if (K_{dc}+K_{harm})>0, then I_{x(avg)}_{_}_{nb} is inversely proportional to V_{d}. This shows that when V_{d}>0, that is, U_{1}>U_{2}, I_{x(avg)}_{_}_{nb}<0, then I_{C1}_{(avg)}<0, l_{C2}_{(avg)}>0, the capacitor C_{dc1} will discharge and the capacitor C_{dc2} will charge until the voltages of the two are equalized; when V_{d}<0, the same is true. This use of topology and SPWM modulation characteristics to achieve capacitor voltage balance is called self-balance characteristic, of course, this self-balance characteristic is established under the condition of (K_{dc}+K_{harm})>0.

Therefore, it is necessary to discuss the situation of (K_{dc}+K_{harm})>0, that is, what factors determine (K_{dc}+K_{harm})>0. Figure 2 shows the self-balancing characteristics of 3L-NPC and the source of self-balancing current when Z_{eq} is a load of different nature. In Figure 2, i_{i}_{nv}(t) is the output current of the inverter bridge arm, which can be seen in combination with equation (1.9). out:

①Except for Z_{eq} which is purely capacitive, the 3L-NPC topology has the characteristics of capacitive voltage self-balancing, and the pure capacitive load condition does not exist, because the actual circuit has a certain parasitic impedance;

②According to the relationship between |Z_{eq}(jω)| and ω according to different load properties, combined with the frequency spectrum of S_{d} in Figure 1, S_{d_dc} and S_{d_10} (at f_{s}) are larger, then the magnitude of I_{x(avg)_nb} mainly comes from the DC component of i_{i}_{nv}(t) and even harmonic components near the switching frequency;

③Usually, the filter has a greater effect on the attenuation of the switching frequency sub-harmonics, but has no effect on the DC component, so the DC component of i_{inv}(t) is also reflected in the load current i_{o}(t), then:

Therefore, the DC component of the load current io(t) is proportional to the capacitor voltage difference V_{d}.

In summary, under open-loop operating conditions, when the voltage of the 3L-NPC capacitor is unbalanced, except for the case where Z_{eq} is purely capacitive, a DC current opposite to the capacitor voltage difference V_{d} will be generated in the capacitor current. This current will eliminate the capacitor voltage difference. This characteristic is called self-balancing. The self-balancing current mainly comes from the DC component of the bridge arm output current i_{inv}(t) and even harmonic components near the switching frequency.

In order to fully illustrate the self-balancing characteristics of 3L-NPC, simulations were performed under the conditions that the fundamental impedance of Z_{eq} is approximately purely resistive, resistive-inductive, resistive-capacitive, purely inductive, and purely capacitive. Figure 3 shows the open-loop simulation waveform when Z_{eq} is a purely resistive load. Figure 4 shows the open-loop simulation waveforms when Z_{eq} is of different load properties. It can be seen from Figure 3 and Figure 4 that due to the deviation of the capacitance value, the initial value of the capacitor voltage has a deviation. When Z_{eq} is operating in open loop under pure resistive, inductive and capacitive loads, u_{C1} keeps decreasing and u_{C2} keeps increasing until the capacitor voltage is balanced, and the equilibrium state is maintained to work, realizing the self-balance of capacitor voltage. Among them, when Z_{e}_{q} is a purely inductive load, it is easy to cause low-frequency oscillation; when Z_{eq} is purely capacitive, u_{C1} and u_{C2} are basically unchanged, and the capacitor voltage cannot be balanced. Fortunately, in actual circuits, purely inductive and purely capacitive loads do not exist.